The G.729 Voice Codec Algorithm And Its Dsp Implementation

The G.729 speech coding algorithm which is based on CELP model is adopted by ITU-T in 1996. It adopts the conjugate-structure algebraic-code-excited linear-prediction (CS-ACELP) and is one of most optimized algorithms concerning coding rates and speech synthesis quality. This coder is designed to operate with a digital signal obtained by first performing telephone bandwidth filtering of the analog input signal, then samping it at 8000 Hz, followed by conversion to 16-bit linear PCM for the input to the encoder. The output of the decoder should be converted back to an analog signal by similar means. The encoder analyzes every single frame of speech signal and extracts parameters (coefficients of linear-prediction filter, codebook index and gains of adaptive codebook and fixed codebook),then transmit them to the decoder in the form of bit stream. But high computational complexity and huge storage capacity are its inherent defects. In the past years, the technology of digital signal processor (DSP) has developed rapidly. DSPs are wildly used in speech coding for its predominant performance and offer a powerful tools. It makes it possible for the real-time implementation of the G.729 speech coding algorithm.This article reviews the most popular speech coding theory and technology, such as the mechanism of voice, mathematic model, short time analysis, linear prediction technology; the basic principle of G.7298kbit/s CS-ACELP speech coding algorithm is studied. At last, steps and optimization methods of real-time implementation of the G.729 speech coding algorithm on TMS320VC5509 which is a fixed-point DSP is deeply discussed. The input and output of analog speech signal are achieved using a high-quality speech codec, TLV320AIC23 which is manufactured by Texes Instrument (TI) and should be correctly configured by sofeware according to the requirement of input signal for G.729 algorithm. The sofeware consist of two parts, hardware initialization and encoder. Because of space limitation, this article only gives a simple decription of hardware initialization, and then gives the detail instruction of optimization methods that adopted by this article, highlighting improving the implementation efficiency. After optimization, the clock cycles taken to encoder a 10ms speech frame (80 samples) is only 517573. On the condition of CPU clock frequency at 144 MHz, time taken to encoder a speech frame is 3.59ms. The experiments show that the results of the optimized algorithm are correct.