Research For Implementation Of Pitch Detection Algorithm In MELP Using FPGA

Low bit rate speech coding has been the very important research direction and hot topic in the area of speech communications. In the low bit rate speech coding area, the mixed excitation linear prediction(MELP) algorithm plays an important role among various algorithms, because it is not only the federal standard of US, but also it has become the main reference algorithm for the developing of other low bit rate and even very low bit rate speech coding algorithms, which have been used in many speech communication systems.When used in practical applications, the MELP algorithm needs a proper platform for its implementation, because this has a great impact on its performance. So far, most implementations of the MELP algorithm have been carried out on different DSP processors.With the fast development of manufacturing technique of FPGA, the scale of an FPGA chip has reached ten million gates in recent years. As a result, the FPGA platform can be used in many digital signal processing areas and of cause speech communication systems.Pitch period is one of key parameters in MELP algorithm and has a direct impact on the quality of the synthetic speech. The purpose of the pitch detection part, which plays an important role in MELP algorithm, is to calculate the pitch periods of speech frames.Although the implementation of pitch detection algorithm in MELP with FPGA platform is difficult because of its higher complexity, but just because it is so important in speech coding algorithms, it is chosen as the study object of the thesis. Firstly, as of the theoretical basis, the encoding and decoding procedure of MELP is briefly introduced and the procedure of pitch detection is analyzed in details. Secondly, the FPGA platforms and the ways of using them to design the specific algorithms are discussed. Then, starting from the fixed-point C program language of MELP pitch detection algorithm and based on the understanding of the MELP pitch detection principle, the Verilog HDL based pitch detection algorithm in MELP for FPGA platform is designed and finished.The bottom-up design procedure has been used while building the Verilog module of the pitch detection algorithm in MELP for FPGA. The thesis builds the modules from the basic bottom layer units, such as the adder unit and the multiplication unit, to more complicated top layer units, like the modules to calculate the integer pitch period and fraction pitch period, and completes the whole module of the pitch detection algorithm in MELP at last.In addition, much optimization work has been done on the designed algorithm modules written with Verilog HDL for their efficient implementations on the FPGA platforms.In order to test and evaluate the design results, the powerful FPGA tool Vivado HLS is applied. The test and evaluation results have shown that all the designed modules in different levels are functioned correct, in the same time, the resource utilization and processing speed are in the reasonable ranges and behave well.