Design Of H.264/avc Decoder Soc

The JVT (Joint Video Team) have developed a new standard that promises to outperform the earlier MPEG and H.26x standards, providing better compression of video images. The new standard is entitled H.264/AVC. The H.264 standard employs several advanced technology such as 4x4 integer DCT, variable block-size, multiple reference frames and quarter-pixel accuracy interpolation, CABAC, In-Loop Deblocking filter.Compared with previous standards, H.264 achieves up to 50% improvement in bit-rate efficiency, but the implementation complexity is also increased at least one time, this greatly challenges its implementation. There are many strategies to implement video decoding system, but three ways are most popular, one is implemented by optimized software on DSP, another is implemented by hardware only, the other uses "CPU + Hardware Accelerater" strategy. It is nearly impossible for a software solution to decode high resolution (eg.1920x1080) H.264/AVC coded stream based on general DSP or CPU given the current technology.This paper proposed an efficient implementation H.264/AVC decoder aiming at Main Profile Level 4 and capable of decoding a 1920x1080 video stream in real time at 30 frames per second. Due to the complexity of architecture, this paper put its emphases on the module of CABAC. The paper also proposes the verification strategy and its implementation.At the time this paper finished, the design of the hardware modules has been completed. It passed the simulation and FPGA verification. According to the decoding speed implemented on FPGA, it can decode real time HD H.264 bitstream.