Study Of Nuca Based On 2d-buses Interconnection Network In Cmp

Cache technology is an efficient way to reduce the speed differences of the processor and the main memory (namely memory wall). Since more and more transistors can be integrated on the single chip, designers can realize the large Cache on chips to enhance the performance. However, the wire delay on the chips keeps increasing in the traditional Cache, which becomes the bottle-neck of the processors.To solve this problem, the researchers proposed Non-Uniform Cache Architecture (NUCA). In NUCA, Cache is divided into several Cache Banks connectting with each other through interconnection network which has impact on NUCA's performance. Most of the present NUCA are based on Mesh, which cannot effectively support the multicast searching in NUCA, affecting the performance of it. This paper proposed a new kind of NUCA based on 2-D buses interconnection network (named 2-D Buses NUCA) by utilizing the effective support of bus for the broadcasting. Besides that, the author also studies about the relevant problems. All the main work is as follows:1. The paper both studies and analyzes theoretically the delay performance of the 2-D Buses NUCA. It analyzes the effect of the hit rate, the node scale and collision rate upon the performance of the entire system. It shows that the 2-D Buses NUCA is affected greatly by both the collision and the size of the system and that it is better to be used in systems of small scale.2. It also studies the key technology about the realization and design of the 2-D Buses NUCA, including: mapping and searching strategies, the switching and routing strategies of the interconnection, the technology for the realization of the Cache Bank, the arbitration of the bus and so forth. This paper analyzes the performance and cost, and thus chooses the most suitable strategies, including regular mapping and searching on bus structure, virtual cut-through, fairly round arbitration, and etc.3. It realizes the Two-dimensional Bus NUCA's system S2DB-NUCA and validates the performance of the system through experiments. The author designs a small prototype system S2DB-NUCA which is realized in Verilog. The experiments to validate the performance of the system by using the Xilinx FPGA chip Virtex-4. Then the results are analyzed and the performance of the system validated. And we find the effectiveness of the access delay model established above.