Testing Of Delay Faults In NoC Interconnects

As technology advances, IC industry has entered the UDSM (Ultra DeepSub-Micro, UDSM) era, The semiconductor device feature sizes continue to shrink, andthe number of blocks can be integrated in a single chip continue to increase. Thetraditional bus-based on-chip communication method have been faced the problem ofpower, performance, latency and reliability, and increasingly unable to meet the needsof on chip communication. In this context, people trying to apply the networkcommunication method to the design of SoC communication structure to overcome thelack of bus-based architecture, and the NoC came into being.Technological progress also makes chip testing difficult. There are greatdifferences in the structure of NoC and traditional SoC, the SoC test method cannotcomplete the NoC test task well. Therefore, there is an urgent need in-depth study of theNoC testing.This paper first introduced the development of Network-on-Chip. Through thestudy of on-chip communication of NoC, completed the following works:1. NoC interconnects delay fault analysis. With the device feature sizes continue toshrink, the interconnect delay become a major aspect of the on-chip delay. This thesisdetails the sources of on-chip delay, and the causes of delay fault, then established theNoC interconnect delay fault model.2. NoC interconnects delay fault diagnosis. Proposed a BIST method to diagnoseinterconnect delay faults. And the test circuit and ATPG module is designed for thismethod.3. NoC delay fault testing simulation. Design the test circuit and ATPG withVerilog HDL, and run simulation with the Modelsim to verify the functionality of thecircuit.4. Hardware verification of the NoC delay fault test circuit. Implementation theVerilog code in Xilinx ISE and generate the FPGA configuration file. Run the testcircuit in FPGA to verify its functionality and performance. Simulation and hardware verification results show that the designed test circuit andATPG module work properly and realize the function of NoC interconnect delay faultdiagnosis; the proposed delayed fault diagnosis method can found interconnection delayfault rapidly and accurately.