Font Size: a A A

Research And Implementation Of Compiler Technology For TTA Processors

Posted on:2011-11-30Degree:MasterType:Thesis
Country:ChinaCandidate:Z L LiuFull Text:PDF
GTID:2178330338481778Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Since the configurable processor can be customized for a particular application, it has increasingly being used in the embedded system design. This thesis presents a method of the compiler back-end optimization for the configurable and extensible processors based on the Transport Triggered Architecture (TTA). The designs and implements of register allocation with linear scan algorithm in compiler optimization are explained. In addition, the thesis presents a new method of how to combine register allocation and instruction scheduling, and has made an implementation.At present, compiler for general-purpose processor has been able to generate very efficient code. But most of the compiler technology is only for a fixed structure. So it is a big challenge in code optimization for configurable processor, and it is also a difficult and important task for the application of configurable processor.Compiler especially its back-end design is the key of TTA processor being used widely. A compiler's back-end optimizing design for TTA processor using linear scan algorithm is presented in this thesis. This algorithm has been used to accomplish global register allocation. The implemantation of this algorithm on TTA compiler has many advantages, such as high quality of code and easy implementation, etc. The advantages of this algorithm are especially obvious when source programs contain large number of variables competing for the limited number of registers for storage. In addition, the thesis presents the study of a series of optimization based on linear scan algorithm. Instruction scheduling is another important step in the compiler back-end design, and the processing sequence between register allocation and instruction scheduling is the key factors for compiler performance. The thesis also proposes a method of combining register allocation and instruction scheduling. By finding a balance point between instruction scheduling and register allocation which are restricted by each other, the quality of the code is impoved. This increases the overall efficiency of TTA compiler.Finally, the experimental results are analyzed and evaluated. And the summary and future prospects are given at the last part of the thesis.
Keywords/Search Tags:Configurable processor, Transport Triggered Architecture (TTA), linear scan algorithm, global registers allocation, compiler's optimization
PDF Full Text Request
Related items