Design Of RSA Algorithm IP Core Based On SOPC

With the rapid development of modern information technology, informationsecurity problems have became increasingly prominent, and have been widespreadconcern in all aspects of society. RSA algorithm is not only used for both messageencryption, but also be used for digital signatures, authentication, so in the field ofsecurity or authentication it is widely used.As the RSA algorithm is very high computational complexity of cryptographicalgorithms, hardware implementation of the RSA is very difficult, that will need a lotof logic gates and circuit area is quite large, practicality is poor. The use of softwareto achieve RSA, computing speed is too slow and achieve efficiency is very low, butalso that reduces the intensity of anti-decryption. The SOPC system can solve thepure software and pure hardware implementation deficiencies and shortcomings,therefore, this paper designed a based on SOPC RSA algorithm IP core. That is tosay: the use of a combination of hardware and software methods to implement theRSA algorithm, is to find the best combination between speed of operation andcircuit resources and to get a better performance.This paper introduces the subject of background, research status, SOPCtechnology, IP core technology and the basics of the RSA algorithm and thealgorithm works. And in-depth study of the RSA algorithm implementation isproposed based on SOPC system design.In the overall design,system is divided into two parts, one part of the software:generate the key pair, as in the encryption and decryption process this part isexecuted only once, so the use of software, will not affect the operation speed, andreduces the circuit resources. Second, the hardware: As modular exponentiation is thecore of the RSA algorithm, which directly affects the operation speed encryption anddecryption speed, so this part is implemented in hardware. This paper details theimplementation of modular exponentiation various sub-modules, and communicationbetween hardware and software interface bus.Finally, the entire system uses QuartusII9.1compilation and synthesis.And itcarried out in the Modelsim SE6.5simulation. The simulation results show that thesystem has achieved the desired goal.