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Algorithms Resarch And Verification Of Multi-channel Communications System

Posted on:2011-12-13Degree:MasterType:Thesis
Country:ChinaCandidate:J WuFull Text:PDF
GTID:2178360308953466Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
A whole algorithm, based on the requirements of multi-channel communications system, is proposed in this paper to implement the transmission and receiving of the signal. The function of the system is performed by using Field-Programmable Gate Array(FPGA) to set up the hardware system and the software to develop after arithmetic simulation. The implementation of the system also lays a good foundation for future work such as algorithms improvements of the receiver.The system comprises of four parts which are signal transmitter, receiver, signal channel and upper computer as a console. The function of the signal transmitter is encoding, filtering and modulating the signal. The devices of A/D and D/A are applied to simulate the channel. In the receiver, the received signal is demodulated after carrier recovery. And the demodulated signal is decoded after timing recovery. The upper computer could be used for real-time control of some key parameters by GUI. The result of the receiver also with the error rate could be displayed on the computer.Arithmetic improvements of the multi-channel system are necessary under the influence of nonstationary signal and background noise. Based on the analysis of requirements, the arithmetic simulations of transmission and receiving of the signal are implemented here. According to the result of the simulation, comparisons of different kinds of algorithms for particular parts are displayed in this paper. The system structure is designed on the basis of arithmetic simulation. Then, by experiments, the multi-channel communications platform could implement high-rate signal processing for real-time by the application of logic units in devices of Xilinx Spartan-3A DSP FPGA and the ip core of microblaze as well as the software suit of ISE to develop and debug.The focus of the paper is on the algorithms and verification of transmitter and receiver. There are illustrations for designing and analysis for performance of important signal processing steps such as carrier recovery and timing recovery etc.
Keywords/Search Tags:multi-channel, IF, carrier recovery, timing recovery, FPGA
PDF Full Text Request
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