Research On The Configurable And Monitored NoC Prototype Platform

With the development of integration scale, designs of bus based on System-on-Chip is confronting some disadvantages, such as poor scalability, lower communication efficiency and a single clock synchronization, etc. In order to solve these problems, a new on chip structure, Network-on-chip (NoC), is proposed, and becomes a mainstream design technology for the next generation integrated circuit gradually. The configurable and monitored NoC not only inherits the advantages of the common structure of NoC, but also greatly improves the flexibility and controllability of the NoC systems. We research the NoC prototype based on the two-dimensional mesh, and focus on the communication architecture of NoC. A new configurable NoC architecture is proposed, and it can implement on-line configuration of the NoC communication network, including the terms of the depth of input buffers, routing algorithm and arbitration algorithm in output channels. An intelligent monitoring system for NoC is also discussed. It is used to evaluate the communication performance of the NoC prototype under the finished configuration. The two performance parameters are average throughput rate and average packet delay. A configurable traffic generator was designed to substitute the processor core for evaluation the performance of the NoC prototype, which can achieve more better evaluation and verification efficiency .The main work and achievement are as follows:1. Researched the configurable and monitored NoC prototype based on the two-dimensional mesh, and focused on the on-line configurability and observability of the NoC communication architecture.2. Designed configurable NoC, including configurations of the depth of input buffers, routing algorithm and arbitration algorithm in output channels.3. Designed configurable traffic generator. It can be used as local node for the configurable and monitored NoC system to complete the verification and performance evaluation experiments.4. Validated the design by experiment. The verification experiment composes of three parts, those are verifications of the configuration system, the monitor system and the configurable NoC. FPGA verification and Modelsim simulation were used here. We used Stratix II EP2S180 FPGA of ALTERA and the design run at the frequency of 50 MHz.5. Designed performance evaluation experiments for the configurable NoC. When the configurable traffic generator was not change, compared the performances of NoCs with different configuration, as well as the same NoC when the traffic generator was configured differently.