A Research For The Task Scheduling Of Embedded MPSoC System

Embedded systems are widely used in various fields of production and life. The embedded systems performance has increased gradually due to the technology developement. MPSoCs (Multiprocessors System on Chip) represent the latest development of the SoCs (System on Chips) technology, that integrate multiple processor cores on a single chip, execute parallel applications to obtain high efficiency, and satisfie the requirements of mobile communications, multimedia applications, network security, and other areas of growing demand for embedded systems.In order to maximize the performance of system, we should partiton the application into threads/tasks, and map these parallel threads/tasks onto the multiprocessor cores. The reasonable parallel task/thread management mechanism must be designed to coordinate the parallel tasks running on each processor core.A task scheduling management of the distributed memory MPSoC is proposed to solve the scheduling threads/tasks in parallel. The large-grained data flow model is used to analysis the media application and data dependency among the threads/tasks. The threads/taks is encapsulated a number of objects with designed data interface. The threads/tasks scheduler manages these objects that are mapped onto the processor cores. The message passing mechanism is used to deal with data commuications among different processor. The real-time operating system-Iota is running on the control processor, and expands a multi-core task/thread scheduler to deal with the scheduling of tasks/threads. Meanwhile, the each slave processor has a proxy directory of the multi-core task/thread scheduler in order to manage the tasks/threads running on every slave processor. MPEG-4 encoder as a case study is discussed and justified the proposed solution.The data communication overhead in one macroblock compute is about 1000 cycles, and the task/thread context switching overhead is about 220 cycles, the application execution speedup is up to 2.3 in the three-core heterogeneous SoC system.