Parallel Implementation Of H.264 Encoder Based On Embedded MPSoC

With the increasing demand on computing power, it is popular in embedded chip field to integrate multiple processors into a single chip, which forms Multi-Processors System-on-Chip (MPSoC).It is dificult to develop parallel software based on embedded MPSoC,for there are several challenges including how to explore the parallelism of original program and to encure the synchronization and communication between parallel tasks/threads while scheduling them on the embedded multi-core system.This paper does a research on parallel implementation of video encoding program in embedded multi-core system, and proposes a pipelined task parallel method for those data stream processing program.This method uses coarse grain data flow graph to denote the process of original program, and search for a efficient partition strategy based on the simulation of the computation of module on original data stream and the analysis of data dependence among modules.If we can't find out a satisfied partition strategy through the current coarse grain data flow graph, the nodes in the data flow graph should be splitted or merged until a satisfied partition strategy is met. Further, parallel task/thread can be scheduled according to a modified director interface standard.After parallel task/thread statically mapped to corresponding processors, directors settled in processors can be executed dynamically to accomplish operations such as task scheduling synchronizing, and communication.This paper analyzes the computation ratio of modules and data dependency among modules in MPEG4 and H.264 coder. Based on the analysis, we devise task parallel partition strategies for heterogeneous MPSoC platforms with 3 processors and 5 processors.Coordinating with modified director, we complement the execution of program on multi-processors.The experimental results show that the average utilization of processors in the MPSoC can be 60%-70%, which asserts the effectiveness of multi-processors'parallel method. This programmable and portable scheme can explore the parallelism of original program and mask the bottom hardware structures.