Viterbi Algorithm Acceleration Based On ESL Methodology

The design complexity of modern integrated circuit systems is outgrowing the capabilities of traditional RTL (Register Transfer Level) methods, ESL (Electronic System Level) methods based on HLS (High Level Synthesis), which raised design abstract level and design productivity, is now gradually adopted by the IC industry. ESL methodology enables the designers to design, verify and synthesize integrated circuit systems at a higher level of abstraction.This paper firstly introduced ESL methodology and flow based on high-level synthesis, including the concept and advantages of ESL methods, TLM (Trasaction Level Modeling) methods, high-level synthesis technology, and put an emphasis on the methods of hardware development based on high-level synthesis. Then we introduced the concepts, principles of Viterbi decoding algorithm in the field of wireless communications, and analyzed algorithm complexity and performance requirements.On this basis, a 3-bit soft-decision (2,1,7) Viterbi decoder based on ESL design methodology is given. We adopted SystemC language to design and describe the ESL model for the Viterbi algorithm. With ESL simulation validation, the algorithm is refined and optimized for high-level synthesis. By adopting a high-speed parallel architecture, the result shows that the decoder achieved higher performance and throughput rate.Finally, after the RTL validation, we put the design through RTL synthesis and automatic place and route, and result shows that Viterbi decoder takes the 2397 LUTs, the area is superior to manual RTL Viterbi IP.