Design And Implementation Of FPGA Based If Multi-channel Communication Platform

With research and simulation of system structure and signal processing, a FPGA based multi-channel communication platform is implemented with SoC method, modular, programmable and portable for both software and hardware modules.System organization, signal structure and basic theory are introduced firstly. The research on algorithm of ASK IF transceiver is implemented with MATLAB for feasibility evaluation. The VerilogHDL based platform is built up with ModelSim for behavioral simulation and system architecture of software and hardware. With results of algorithmic and behavioral simulation, VerilogHDL based hardware modules are gradually refined to register transfer level (RTL) to design and implement synthesized firmware modules and interfaces including clock generator, test data generator, raised cosine filter, carrier generator, AWGN generator, SPI interface, digital PLL, timing recovery, FIFO and etc.. Software on MicroBlaze is implemented for real time control and data communication. Firmware is synthesized, placed and routed with constraint files by Xilinx XPS so that a FPGA and MicroBlaze based multi-channel communication demonstration platform with multi-path effect is built. The communication system is able to send signal, mix frequency, implement digital baseband processing and control signal processing flow so as to provide a good validation platform for DSP algorithms, which could test and evaluate performance of modulation algorithms. In the meanwhile, the capability to send 8-channel IF multi-path signals simultaneously increases the system redundancy and reliability so that partial failure will not lead to the breakdown of the whole system. Verification and compare of algorithm performance can be implemented with different parameters configuration for varied channels.The paper focuses on the design and implementation of FPGA based ASK IF transceiver and detailed design and functional verification are described.