Research And Implementation Of Multi-Channel Technology In Wireless Channel Emulator Based On FPGA

The wireless channel emulator is a kind of instrument which can simulate the real wireless channel propagation environment in the laboratory environment.The wireless channel emulator can perform a large number of tests on wireless devices before they are marketed to ensure that their performance meets the requirements.How to test and evaluate the performance of MIMO system of base station and terminal is very important for the realization of 5G commercialization and the improvement of system capacity and efficiency.Compared with the current 4G network,the number and bandwidth of 5G channel will increase significantly,which will directly lead to a significant increase in the hardware design difficulty and cost of the channel emulator.Therefore,the new high-performance channel emulator must be upgraded accordingly in terms of channel number and bandwidth.This thesis focuses on the research of the multi-channel technology in the wireless channel emulator.In view of the problems in the design of the high channel count wireless channel emulator,the design and implementation of the scheme are carried out on FPGA.The main work of this thesis is divided into three aspects,including:1.Design and implementation of multi-channel amplitude phase mismatch calibration.Aiming at the inconsistency of frequency response between multiple transmit and receive channels in wireless channel emulator,this thesis proposes an improved channel calibration method for channel emulator.This method has the characteristics of fast convergence and higher calibration efficiency and lower calibration cost compared with the traditional calibration method.Before the baseband real-time channel simulation processing,the mismatch correction between channels is completed to ensure that the system obtains higher channel simulation performance in later processing.In this thesis,firstly,the channel mismatch phenomenon of the channel emulator is analyzed and studied;Secondly,the adaptive filter technology is analyzed,and then the software simulation analysis of the method is given.Combining with the hardware resources of FPGA,the Verilog HDL hardware description language is used to model the digital system from algorithm level,gate level to switch level,and to optimize the efficiency and accuracy of the hardware implementation of the algorithm,so that it is easier to achieve automatic calibration on the hardware platform of wireless channel emulator.According to hardware measurement,each channel has good channel amplitude phase consistency after calibration.Compared with the reference channel,the average channel phase error is 1°,and the average channel amplitude error is 1.1514%.2.Design and implementation of noise interference signal generator between channels.In the process of channel simulation,it is necessary to add Gaussian noise that matching with high-speed digital signal rate for the analysis and calculation of the anti noise performance of digital communication system.The noise interference signals not only need to ensure that the noise interference of each channel is independent of each other and the 0.1 dB step gain is adjustable,but also need to be generated in the baseband real-time channel analog processing system easily.In this thesis,the method of approximating Gaussian probability distribution function with center limit theorem and shift register are used to generate random digital AWGN signals,and the multipliers and pre-stored power control coefficients are used to control the AWGN noise power,the statistical characteristics and the output rate of the signal meet the requirements of the simulation system.The specific hardware implementation scheme is given.The theoretical analysis,software simulation and hardware implementation of the signals generated by this scheme are also given.3.Implementation of data stream synchronization mechanism in signal processing board expansion.In order to implement a channel emulator that supports a higher number of channels,the low-level high-speed serial transceiver GTX IP core provided by Xilinx FPGA was re-developed,and a FPGA data stream synchronization mechanism is designed to apply for multi-channel channel emulator baseband data transmission between baseband real-time channel analog boards,it solves the problem of limited resources of a single processing board,and realizes a hardware architecture that is easy to horizontally expand,and meets the needs of high-order channel number channel simulation testing.Functional decoupling and each module completes independent computing functions are achieved by the hardware modularization.At the same time,accurate timing synchronization is achieved between single processing boards by an effective data stream synchronization mechanism.So the channel emulator can be configured that the MIMO test channel number within the hardware channel number range at the software level by the way of cascade expansion.Finally,the overall system joint debugging based on the data stream synchronization mechanism was completed,and a multi-channel Doppler test is conducted.It not only verifies the effectiveness of each module,but also verifies the consistency of multi-channel technology in the debugging test.