The Design And Implementation Of S-band Frequency Synthesizer

Frequency Synthesizer is one of the most important parts in modern communication systems, and it can be widely used in fields such as the communication, military communication system. With the development of modern communication technology, frequency synthesizers are required to have lower noise, higher resolution, faster frequency switching speed and lower spurious.Paper based on direct digital frequency synthesis DDS incentive PLL Frequency Synthesizer PLL technology, through software ADIsimPLL design, analysis and calculation, to achieve S-band frequency synthesizer hardware circuit.The thesis first described the working principle and spurious sources of DDS, discussed the sources of spurious signals from three was phase truncation, quantization error and non-ideal characteristic of D/A. We analyzed the structure of PLL, discussed the mathematical model of PLL and the phase performance of PLL frequency synthesizer.Based on the analysis of the basic theroy about DDS and PLL,according to project, picked out excellent DDS chip AD9958 and PLL chip ADF4106,using DDS incentive PLL frequency synthesizer technology to achieve S-band frequency synthesizer about low phase noise,high resolution,high-switch-speed.We discussed the feasibility of scheme implemention,analysed the main compoments of the circuit and the achievement of the circuit, detailed the circuit module and its important technical means of implemention.Finally,the circuit had been tested.The examination results of circuit show that the performance parameter of frequency synthesizer reaches the design requriments and frequency resolution is 2.32Hz,the out frequency range is 2.3-2.95GHz,the phase noise-94dBc/Hz@10kHz,-108dBc/Hz@1MHz, the spurs level is below -50 dBc, and hopping time is 15μs from 2.3GHz to 2.95GHz.The frequency resolution, phase noise control and frequency hopping time is better than our original design requirements required.