Research Of The E1 Bit Error Testing Technology Based On FPGA

The desktop bit error tester is not suitable for integration testing because of its huge volume, this paper research of the bit error testing technology and its FPGA implementation which used in the integration testing system based on VXI bus for E1. This technology has an important engineering application value.The principle of bit error testing is analyzed, and a scheme of bit error testing technology used in the integration testing system based on the VXI bus and virtual instrument is presented. This paper analysis and calculats the parameters of analog hardware based on the international and national standard.The instrument is consist of power supply, clock generating, VXI bus interface, E1 interface, FPGA control, relay control circuits.The designed principle of PRBS code generating, periodicity random error inserting, synchronization of the local pattern , the HDB3 coding-decoding and the bit error rate testing is work out based on the function of bit error tester. The designed method of he E1 framing-reframing and the CRC checking is introduced in detail. The framer, reframer and the CRC checker is realization based on the bit for bit technology.The instrument realizes all functions required, shows a good performance of facility and stability and passed national authentication.