Research And Implementation Of Multithread Processors For IP Packet Processing

Research of the architecture of multithreaded chip multi-processor (CMP) with throughput-oriented optimization is an important domain on performance of the network processors. To enhance processing performance of data path of the network processors, A multithreaded application-specific instruction processor (ASIP) core is designed and implemented on the FPGA platform of Xilinx Virtex-II PRO xc2vp30. The processor utilizes an instruction set optimized for IP packets processing and a 5-stage pipelining RISC processor as its baseline architecture. To improve the packet processing capability of single thread in the processor, the blocked multithreading architecture (BMT) is exploited, and a static thread switch policy based on Round-Robin arbitration algorithm is adopted for guaranteeing executive fairness among the threads in the core. This architecture loweres the hardware context-switch overhead to zero or one cycle.The inclusion of multithreading within a processor complements the use of multiple processor instances by enabling multiple execution contexts to share a single processor with fast hardware-supported context switching, in addition to having multiple contexts executing in parallel on distinct processors. Synthesis results obtained using Xilinx Virtex-II PRO xc2vp30 show the multithreaded core has 3 times the performance of the baseline structure, while chip area increases only 7%. So this processor core can be exploited in architecture exploration of high performance CMP for improving processing capability of IP network and access device.