The Study Of The Architectures And Implementation Technologies Of Multi-PEs Network Processors

Network processors are the key devices to do packets forwarding in the routers. As there is inherent parallelism in the packets processing, network processors adopt many parallel technologies to accelerate the processing of the packets. The parallel architectures of the network processors are explored in this article and the parallel technologies adopted by the network processors are divided into three aspects. They are the parallelism inside the PEs(Processing Element), the parallelism between the PEs and the parallelism between PEs and coprocessors. The features of network processing decide that the parallelism inside the PEs is not the main direction of development. So the emphases are put on the key technologies of the last two parallelism methods.Based on the analysis of the parallel technologies adopted by the network processors, a YHNP network processor and it's architecture are presented. The main data paths and functional units are designed in detail. All of them are described with Verilog language and passed in ModelSim5.5.Then several key problems in the design of YHNP network processor are discussed. These problems mainly include the scheduling of PEs and the packets dispatching strategies. Abstract is made to the packets processing model and a generic timing model of packets processing is presented. A simulator of such a timing model is implemented with C++ language. With both mathematic analysis and programs simulation are used to study the key problems mentioned above. The principle and implement methods of PE scheduling and a effective and simple strategy of packets dispatching is achieved.