| VDMOS field effect transistor is a particularly popular recent power electronic devices, it has a high input impedance, low drive power, high frequency, wide safe operating area of the excellent electrical characteristics, and be able to compatible with the CMOS production process, production process is simple. Therefore VDMOS FET widely used in switching power supplies, AC-DC conversion, motor control, RF communication, audio amplifier, high-frequency oscillator, uninterruptible power supply, energy saving lamps, inverter and other areas and can be carried out with the CMOS bond to form the intelligent power semiconductor chip to form a specific function of SoC.With the power semiconductor technology, the use of power semiconductor devices power supply allows people to be able to apply a low-power portable devices to communicate anytime, anywhere; use of power semiconductor devices energy saving lamp ballast energy saving lamps can save power consumption of the country save a lot of energy and non-renewable resources. But more and more powerful portable devices and new energy-saving technologies for power semiconductor devices of power put forward higher requirements. These requirements embodied in the high voltage and low power consumption, so that the study of its resistance and the pressure become necessary. Resistance and the voltage is proportional to another, this needs to be a compromise here. Chen Xingbi academicians who have carried out a detailed theoretical study, the conclusion that the pressure and the resistance between the best relationship that silicon limit, which was later VDMOS silicon designers to design a theoretical basis and goals. And later to break the silicon limit restrictions, continue to the birth of a new structure of silicon, so that pressure rising, while the resistance decreased continuously. On the other hand, using a very wide band gap silicon carbide can withstand further enhance the VDMOS structure. So VDMOS very bright future for research VDMOS is also very necessary.The method of VDMOS is in addition to theoretical analysis of the experiment to quantify its description. Previous experiments with different batches of different structures, different pressure, different terminal structure of VDMOS for clean room production, such complex experimental procedure, experimental repeatability is low, long production cycle, the overall cost is very high.With the physical model of semiconductor devices, process and device physical model calculation of the in-depth research, coupled with the proliferation of computers, today's semiconductor device manufacturing to test the entire process can be simulated with computers. Computer aided software process simulation and device simulation, greatly facilitate the device design process, shorten the design cycle, reducing design cost. This is the current mainstream semiconductor device design method, this paper used the three process and device simulation packages of SILVACO for semiconductor power devices designed and conducted a virtual electrical test.By analyzing the VDMOS the pressure and resistance and the relationship between pressure and the terminal structure, quoted Chen Xingbi Academy of silicon limit theory,600V VDMOS a detailed device design and process design, and through sections of the device simulation software authentication device structures, but also by process simulation process, the final design of the production process of a VDMOS and VDMOS device structure.First of all, to chip the surface efficiency of the design of cellular shape, select the square, the next level from the process conditions and the impact of channel length on the pressure were considered, the design of cellular size. Theoretical limit of silicon determined by cellular VDMOS the epitaxial layer doping, epitaxial layer thickness and characteristics of resistance.600V resistance from the part of it can be all part of the resistance operations, anti-body area junction depth introduction of P, P +junction depth and the source node N+junction depth and doping concentration of the knot. Through three simulation software for the design of the first device was verified, showing that the design meet the requirements. Also through the process of theoretical model for the VDMOS production process was designed and carried out by three process simulation software to simulate manufacturing, can be proven to withstand 700V, the threshold voltage of 1.55 V, can be achieved design requirements of this article.While this paper presents three innovations:First, for the first time using the physical model of semiconductor process to guide the design of semiconductor process and computer simulation. Through this thesis to study mature VDMOS process, an oxidation, etching, diffusion, ion implantation, film deposition and other physical models to estimate the required parameters and get virtual results by computer simulation.Second, instead of real chip experiment, we use computer aided design software to virtually manufacture VDMOS and test which is more chip and short design period.This study for the realization of power semiconductor devices of virtual manufacturing and virtual tests are an important reference for shorter design cycles, reduce design cost and a positive sense, has great potential for commercial applications. |
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