A Study Of High Power VDMOS Model Based On MET Model

Power VDMOS device(Vertical Conduction Double-Diffused Metal Oxide Semiconductor) is one of the power electronic mainstream products. With its higher input impedance, wider safety operating area, faster switching speed and better thermal stability than other general power transistors, VDMOS is used widely in the switching power supply, motor drive, energy saving light, automotive electronics, and so forth. in recent years, China has made progress in the research of VDMOS power devices, but still it is not very mature, and a lot of the VDMOS products in China need to be imported from foreign country, so it has very important practical significance to the VDMOS device characteristics research, and the device modeling, also the model optimization.This thesis selects and uses the VDMOS device, developed by one Semiconductor Technology Company. On this thesis briefly we introduces the application of VDMOS, its development prospects and significance of the VDMOS model research. An all-overview of the relevant model theories then is presented, including the SPICE model and its development, also the main characteristics of the MET model and device physics mechanism MET mainly considered. Next the device test system, modeling simulation software, the detailed and comprehensive model extraction steps are introduced. The development of VDMOS structure then is described, The DC characteristics, the thermal temperature characteristics and the dynamic capacitance characteristics of power VDMOS device are analyzed. Finally, the DC test and dynamic capacitance test on VDMOS are done, including the output curve, the transfer characteristic curve and the capacitance curve with the bias voltage variation, the VDMOS model is created with some special simulation software. In the process of modeling, it is found that the initial MET model can not characterize VDMOS well, because it is mainly oriented to low voltage and low power MOSFET device. Therefore, based on the MET model, the sub-circuit model is proposed, adding a resistance in the drain controlled by the gate voltage and drain voltage, to well fit the VDMOS test data, and to improve the VDMOS model accuracy. At the same time this thesis makes some changes to the Verilog-A model file of the MET, modifying the original equation code with in Verilog-A, adding several parameters mainly used to fit the linear region and saturation region of the IV curve. The simulation curve with the optimized MET model shows that it is consistent with the actual VDMOS characteristics. For the CV curve fitting, mainly this thesis approximates the measured CV data as a piecewise function, and then expresses the function with the sub-circuit form, finally simulates the sub-circuit model by Cadence. It is found that the fitting accuracy of the sub-circuit model is high, and the error between measured data and simulated data is measured by Err data. Typical device Err data at Id-Vg circle is Err:MAX=100%|RMS=16.96%,and at Cgd-Vg circle is Err:MAX=22.43%|RMS=3.001%.