The Studies On The Reusable Design Methodology Of Multi-mode Video Decoder And The Implementation Of Motion Compensation

In the past ten years, many researchers around the world have engaged in improving the video compression technology and have developed many audio video codec standards. Several standards will coexist after a long going development. The same development exists in the semiconductor manufactural technology and integrated circuits design methodology. Theminimum size of the integrated circuits has turned from micron to nanometer, high levelsynthesis technology becomes the symbol of the EDA's new era and lots of high integration design methodology such as SoC, NoC comes into application. Following the entirely development of integrated circuits technology, a chip that can configure to support several video standards is available and is the best scheme for the multi-standards coexisting market.By the time of the new video compression technologies are printed, several efficient simple technologies become the common base of every video codec standards. The DPCM that is adopted by H.264/AVC and AVS is one of them,The common technologies and the comparison between the two standards are analyzed in chapter 2. The detailed comparisons in motion compesation between the two standards are gived for the algorithm reusing in chapter 3.The gap between design ability and manufacturing productivity keeps on increasing. It promotes the design methodology. We will review the history of the IC design methodology, universal design flow, all kinds of optimization methodologies and implementation methodologies in chapter 4. These are the guidelines thoroughout this project.The reusable technology guides my design from system design to block design. In chapter 5, it introduces the reusable design of motion compensation module detailedly. Because the optimization in higher abstraction level has higher efficiency, we optimize and reuse the design in higher level firstly. Then, we use parallelism and pipeline technologies in every sub-module's design. We also can optimize the usage of third party's IPs. This paper uses multiplier IPs as an example to introduce the reusing and optimization methods of IPs. The reuse technology of on-chip memory is a high efficient method to reduce chip's area and power consumption, so a new efficient management of on-chip memory was inctroduced in chapter 5.