FPGA Verification And Optimal Design For Image Compression System Based On JPEG2000

With the development of Internet and mobile communication,the size and transmission of images are getting bigger and bigger,which brings pressure to the limited transmission bandwidth and storage space.Image compression technology is the key to solve this problem.JPEG2000 is widely used because of its high compression performance and excellent characteristics and consists of two modes of lossless compression and lossy compression,in which lossless compression has important application value in areas such as satellite image transmission,medical image and Internet image transmission.At present,the study of JPEG2000 lossless compression system is mainly focused on its hardware implementation.This paper presents a JPEG2000 image lossless compression system based on field programmable gate array(FPGA)hardware structure.In this paper,the design principle of core module such as raw data preprocessing,discrete wavelet transform,bit-plane encoder and arithmetic encoder in JPEG2000 image compression system and FPGA-based hardware implementation are analyzed in detail.The improved algorithm of the 5/3 reversible filter for lossless compression is applied to the discrete wavelet transform and the hardware structure of the three-stage pipeline is used to design the wavelet coefficients.The three scanning channels parallel processing way is adopted in bit-plane encoder and the coding rate is improved.A cache mechanism between the context of the CX and the D decision is established so that the results of parallel processing can be ordered output to the next module.The hardware structure of the five-stage pipeline is designed in the arithmetic encoder and the maximum and minimum probability interval coding are selected by the state machine switch.The correctness of the function is verified by the modelsim simulation tool.The XILINX model 6vlx240tff1156-2 FPGA chip is used and the HDL project is synthesized in the ISE 14.7 development environment.As a result,the resource utilization is 21%and 13,229 Flip-flops.Operating on the opetating frequency of 100 MHz,the error is inferior to 6%comprared with the software compression in the 20:1 compression ratio of sample images compression,while the compression rate increased more than 2 times,and the product qualitafication is achieved.