FPGA Design Of JPEG2000 Core Encoding Algorithm

Image compression techniques are very important for the storage and transmission of the huge data in the image processing. The traditional still image compression techniques, such as the well-known JPEG standard, can not meet the demand for the compression images quality further improved in various emerging applications. The latest still image compression standard JPEG2000 adopts discrete wavelet transform (DWT) and the bit plane arithmetic coding, which achieves much better coding efficiency and image quality than the traditional methods. With its excellent performance and prominent features, JPEG2000 will no doubt become the main-stream in the image compression field in the future. JPEG2000 ASIC has been successfully developed and applied but there is still a limit. For these reasons this paper deeply studies hardware technique based on wavelet transform and the bit plane arithmetic coding in JPEG2000 standard.This paper focuses on the core modules of the algorithm based on the lifting scheme of discrete wavelet transform and the bit plane arithmetic coding, then improves software algorithms process and presents a VLSI construction. This paper completes logical functional segmentation and module division of the core modules in a top-down design way, and achieves the sub-module design and the final design of the whole system.This paper presents a line-based two-dimensional discrete wavelet transform parallel structures to avoid the traditional serial structure starting column transform after the row transform finishes in the two-dimensional wavelet transform structure. In the structure, the row transform and the column transform are running simultaneously, in other words, the column transform starts immediately after two row transform finished, which makes the efficiency of wavelet transform improved markedly. Using the hardware description language VHDL, this paper finishes the simulation and logic synthesis of the sub-module function and verifies the feasibility and effectiveness of wavelet transform design structure with FPGA.In the design of the bit plane arithmetic coding, to reduce the complexity of the algorithm, improve the efficiency of encoder and reduce the hardware size, this paper improves the bit plane arithmetic coding algorithm, then gives a structural plans consisting of the probability index, the probability update, encoding and output modules, and completes the overall design and simulation of encoder. The simulation indicates this method using FPGA has certainly improved arithmetic coding efficiency.