Research On Multi-layer Random Stimulus Methodology Of Microprocessor Verification

With increasing complexity and shorter producting time, functional verification of the large digital design, especially microprocessor, is a chanllenging problem which will cost large amounts of effort. One of the main research directions is exploring the simulation-based verification method. This thesis presented a new multiple-layer constraint random stimulation generation technique to increase function coverage and stimulus validation and improve the efficiency of processor verification. The original contributions of this thesis are as follows:1. Layered constraint random technique. It combined the advantages of strong targeted in directed stimulus and the convenience in general random stimulus through the layered architecture. It also realized the abstraction from bottom physical layer to top system layer to improve the quality and effectiveness of stimulus. Multi-layer constraints from four layers, test, scenario, function and command, can strengthen the controllability on random stimulus generation in different granularities, and refine the stimulus space to speed up the whole verification work.2. Configurable function library technique. Based on those fundamental functional behavior units of microprocessor, a new configurable function library was proposed to generate two kinds of random stimulus for internal logic function and external communication interface respectively. It ensured the orthogonality of processor computing and communicating functions to build the actural processor application environment and expand the test space. Function Library separated function realization from test case which reduced the number of test vectors and had better reusability for series processor verification.The multi-layer constraint random stimulation generation technique has been successfully applied to CKCore microprocessor verification platform. As shown in CKCore microprocessor verification experiments, compared with traditional constraint random stimulus generation, the proposed strategy can effectively improve the quality and efficiency of microprocessor verification, with 60% stimulus coding reduction, while more than 10% and 5% function and code coverage increase.Techniques proposed in this thesis had positive effects on improving the efficency and function coverage of microprocessor verification.