The Research On Automatic Generation Of Functional Verification Program For Microprocessor Based On Constraint Solving

Today, with the microprocessor being more and more complexity, functional verification is widely acknowledged as the bottleneck of microprocessor design. Architecture-level verification can find failures in design flow early, which can greatly reduce loss. Simulation is still the main vehicle for architecture-level functional verification. But the generation of test program for simulation by hands is very low efficient, and its failure probability is high. Therefore, the automatic generation of test program plays a major role in the verification of modern microprocessors.Existing test program generators can't verify the whole design. Their methods for making architecture model are complex. What's more, most of them can be intrinsically ranked automatic random test program generator, which results in low verification efficiency.Based on our own framework for microprocessor architecture-level test program generation, the thesis completes the following work:Firstly, we design a constraint description language with simple syntax and easy expressions and implement the compiler. Aiming at all kinds of constraint instances in architecture level functional test, it can describe the constraint requirement clearly. At the same time, we implement a compiler for the constraint description language, which is independent of architecture variation. With constraints description and instruction model library, the compiler generates C++ codes for constraint solving. After compiling and executing the generated C++ codes, it will finally generate test programs for architecture level verification.Secondly, we research the strategies of instruction generation and integrate all the strategies into the constraint solver. For functional verification requirement, we design the strategies of instruction generation, including: abstracting constraint from instruction set, modeling the constraint net, modeling the control hazard, avoiding the infinity loop, modeling exception, modeling memory.Thirdly, we research the Pipeline State Coverage and implement its arithmetic. Pipeline State Coverage reduced test program sizes. The model of Pipeline State Coverage is presented in this paper.Fourthly, we research the architecture level test program generation of DLX and LEON2 processor. In this case, we plan the verification using constraint description language to test coverage and discover errors which we introduced.The prototype system - MA~2TG can not only generate test program randomly, but also generate specific test program. It has been successfully applied to the verification of DLX and LEON2 processor, and the experiment results have proved the validity of our method.