| H.264 is a new generation video encoding standard constituted by ISO/IEC and ITU-T. H.264 is the most advanced video encoding standard currently. H.264 has a wide application and can be satisfied with different network environment. For instance, standard and high definition TV,ceil phone and digital camera,IP visible telephone and so on. At present, the multimedia service has a wide application in consumption field. Video sequcences can be decoded by software in real time when CPU must run at 300Mhz～400Mhz. That will result in the power increase highly. With the fast development of large scale integrated circuit, The integrated circuit chip has less dimension but high stability and low cost. We can conclude that developing H.264 decoder by integrated circuit technology has a significant application prospect in consumption field.The main object in this paper is to design the H.264 hardware decoder IP core which is applied to mobile equipments in consumption field. After analyzing the H.264 decoding algorithms in detail, this paper divides the hardware architecture into three module according to the different function, and points out detail hardware implemetations of Ping-pong buffer,FSM and image information analysis in Bitstream controller module. After that, this paper designs the strategy of parallel computing and the whole architecture of H.264 hardware decoder IP core. Because image reconstruction module includes large of calculating which has important impact on area,performance and power consumption of ASIC. This paper take a careful research and design on this module. Three hardware architecture are pointed out for IQIT,inter prediction and intra prediction.In IQIT module, after analyzing algorithm of IDCT, this paper points out a hardware architecture to multiple a computing module between 1 dimension IDCT and 2 dimension IDCT. In invert quantification calculating, this paper change the size of rescale look up tables according different pixel locations. The purpose is to decrease the resource of look up table on chip.For the balance of performance and power consumption, a calculating pipline which is generated by gate clocks is presented. This timing structure can increase computing ability and decrease power consumption.In inter prediction module, this paper adds an interpolation control module to select computing data output and register the results of computing because of the complicated algorithm. Other calculating modules work under control signals. This architecture can simplify the process of inter predict computing. The number of reference pixels for 6 coeffs filter and chroma interpolation are the same. For this reason, it multiple data lines to decrease the resource of system band width. According to the data stream in interpolation control module, a 5×4 storing matrix is substituted for large of filp-flops in the algorithm of H.264 standard. The first addition factors in linear computing are stored in 5×4 storing matrix according different kinds of interpolating locations. After the second addition factors are getted, they can be added by the data in 5×4 storing matrix directly.In intra prediction module, non-plane mode prediction is adopted to wipe off space redundancies of current picture and improve the coding efficiency.According to the characteristics of intra prediction, a reconfigurable hardware decoding architecture of which combine the same operation in different prediction modes is proposed. In plane mode prediction, an optimized method which is based on implementation of hardware is proposed. Every intra predicted value can be obtained by a foundation value according horizon and vertical index. This architecture compresses the hardware implementation area and also improves the module utilization efficiency.On FPGA platform, The IP core has passed the RTL level and gate level simulation. It meets the quality and speed requirements on basis of baseline profile of H.264 with 30 fps and the resolution ratio of 352×288 when the frequency is 10MHz... |
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