Research On Technique For Implementing A Neural Network Image Compression Algorithm With FPGA

Neural network image compression is one of the major research directions in the fields of image compression and neural network. The compression algorithm based on multilayer feedforward neural network is the most representative one in the neural network compression algorithms. Supported by a national scientific project, this thesis researches on a hardware implementation of such algorithms, it has a great theoretical and practical value.This thesis mainly investigates the technical questions in implementing this neural network image compression with FPGA (Field Programmable Gate Array),proposes a technology solution of implementing a neural network image compression with FPGA, and designs the key modules in the solution. It also gives the details of the design idea, the module structure and the hardware timing simulation results.Firstly, this thesis introduces present status of neural network image compression, studies the theories of three-layer feedforward and BP algorithm. It gives the image compression and decompression algorithm based on three-layer feedforward BP network, chooses proper transmission function and trains the neural network with some images. At last, the article gets the key parameters of the network to finish the BP network design for image compression.Secondly, this article compares the major hardware solution according to the image compression and decompression algorithm based on three-layer feedforward BP network. It demonstrates the advantages of implementing with FPGA and presents a technical solution of implementing image compression algorithm with FPGA. Then, the thesis studies the circuit design ideas and design structure of the key modules in the solution with FPGA,it puts forward the corresponding improvements according to universal design method, gives the timing simulation waveforms and the FPGA schematic diagram of image compression algorithm. Finally,the analysis and hardware simulation results show that the neural network compression solution with FPGA in this thesis is realizable, practical and advanced. It has an important reference value to relevant study works.