| Accompany the development of the micro-electronic, the performance of CMOS image sensor is becoming better, and several companies have developed high speed and resolution products, such as Cypress Company which designed a kind of sensor whose resolution and speed has achieved 1280 by 1024 and 450 frames/second. But the traditional image acquisition system is not capable of the high speed image sensor's performance. In the view of this, a high speed real-time image acquisition,compressing and data transmission system based on FPGA and USB2.0 is designed in this paper.Based on several image compressing system, this paper puts forward a general planning of the system which uses programmable logic device as controlling chip of the image sensor, makes use of LVDS(Low Voltage Differential Signaling) for data transmission, employs programmable logic device for image compressing, utilizes SDRAM for image frame storage. At last the system realizes communication with PC via USB2.0.Firstly, hardware circuit of differential clock and ADC module is designed in the paper. Then it introduces fundamental situation of LVDS, and gives methods of connecting interface circuit with FPGA and other interface, in the mean time process of wiring and design riquirement are given. Secondly, means of image frame storage by SDRAM and hardware circiuit for it are provided. Thirdly,it designs hardware circuit of USB2.0 interface. At last, hardware circuit of level switch and controlling of image sensor is completed.In the paper, programmable logic device is designed by using Verilog HDL to accomplish control of the image sensor. And it designs controller of SDRAM based on FPGA. Besides, it provides method of parallel-to-serial converting by using programmable logic device through analyzing traditional converting circuit.In the end, results of hardware debugging and software emulation are given, and it analysis performance of the system, which lay a good foundation for further development. |
PDF Full Text Request