FPGA Design And Implementation Of Fibre Channel Adapter

Based on analysis of fibre channel framing and signaling protocol,the architecture and work principle are reseached. After that, it gives a blue print of the implementation of fibre channel adapter with SOPC(System On Programmable Chip) method in FPGA(Field Programmable Gate Array) devices. NIOS II processor, DDR SDRAM controller, CFI(Common Flash Interface) FLASH controller,interval timer, JTAG UART and Fibre Channel interface logic with Avalon bus interface are all integrated into a single FPGA chip,so a full feature SOC(System On Chip) is built.The design of Fibre Channel interface logic uses VHDL hardware description language,and implements FC-0, FC-1 and FC-2 low layer functionality. The data path width of Fibre Channel interface logic is 16-bit.1.0625 Gbps or 2.125 Gbps Fibre Channel applications,point-to-point topology and Fabric topology are supported. FC interface logic uses a SFP optical transceiver and a Stratix GX transceiver to implement the transceiver defined in FC-0 layer. FC interface logic implements 8b/10b encoder/decoder,transmission word aligner,transmission word validity detector,primitive recognition,receiver state machine and FC port state machine. Date received by FC-1 layer should be delivered to upper layer only when the receiver state machine is in synchronization state. Frames could be sent or received only when the FC port state machine is in active state. FC interface logic implements frame reception/transmission and buffer to buffer flow control in FC-2 layer. Frame reception engine can handle all kinds of frame reception termination condition. Frame transmission engine can assemble data offered by upper layer into standard FC-2 frame format to send.FC interface logic is connected with Avalon switch fabric via a Avalon slave port and a Avalon master port. NIOS II processor accesses register space on chip via the Avalon slave port.Fibre Channel interface gives a interrupt signal to NIOS II processor via the Avalon slave port,and accesses DDR SDRAM via the Avalon master port.Hardware description language code ,logic synthesis and place and route process are optimized in order to improve system performance.A board-level platform is built to finish function validation and performance evaluation of the fibre channel adapter.