| Digital signal processor (DSP) is a kind of high performance CPU, which processes signal and image real-time. It is widely applied to communications, domestic appliance, aviation and spaceflight, commercial measure,biomedical engineering and military affairs. At present, DSP is faced with a new challenge in portable application domain, such as digital communication. It is all-important to design a DSP, which is low power, low price and relatively high performance under limited power.With the development of application requirements, in order to realize communication between digital signal processors(DSPs) and various peripheral serial equipments, more and more DSPs are configured serial interface on chip. Serial interfaces has developed from the standard serial port to multi-channel buffered serial port containing numerous function expansion modules. It not only provides high-speed, full-duplex serial communication capabilities, but also supports wireless communication applications such as voice processing and the SPI protocol. Configurable multi-channel buffered serial port has become one of important chip peripherals of high-performance DSP.Based on the background of the FT-C55LP project, multi-channel buffered serial port design and implementation have been studied here. According to the overall hardware architecture of the serial port and the design features of the DSP, this thesis has finished RTL-level hardware circuit design and implementation of the serial port, which includes serial data transmitter and receiver modules and extended function modules. The serial port supports multi-channel buffered mode and the clock stop mode(SPI).The low-power design and critical path optimization have also been paid attention to. Finally the verified results have shown that the functions of the designed multi-channel serial port is basically correct, and the transmission rate can be up to 35 Mb/s. |
