Research On IFF Mode S Burst DPSK Signal Demodulation Arithmetic And FPGA Implementation

Identification Friend or Foe mode S burst DPSK signal contains a lot of state parameters of plane, therefore, to intercept and capture such signal and translate it, a great deal of valuable information can be obtained. But the precondition is to detect and demodulate the signal. Favorable detection algorithm and demodulation algorithm have direct relation to the integrality and validity of the information obtained. The paper relies on some plane carried electron signal receiving and processing system item, combines with the characteristic of the IFF mode S burst DPSK signal, mainly researches the demodulation algorithm, and its implementation based on FPGA. The main work and research fruits are given below:(1) Based on the keystone of energy detection algorithm, the paper has made some proper improvement on it and then put forward an IFF mode S burst DPSK detection algorithm. The energy gate limit of the algorithm can change by following the channel's change, so it has certain self-adaptation ability. Its detection performance and bit error rate all excel over the original one.(2) The paper has improved on the QPSK carrier frequency excursion estimation algorithm proposed by S.BELLINI, and then put forward an IFF mode S burst DPSK carrier frequency excursion estimation algorithm. The characteristic of it is using the difference of the signal's angle but not the signal itself to estimate the carrier frequency excursion, so it is easier than the original algorithm and improves the performance for carrier phase difference estimation.(3) The paper has chosen the Gardner algorithm to estimate timing error, and made some improvement on it, put forward an IFF mode S burst DPSK timing recovery algorithm. The algorithm not only keeps the excellence of the Gardner algorithm, but also reduces the dithering error of the timing loop.(4) The paper has researched the IFF mode S burst DPSK signal's demodulation system structure. Through cooperation with sorts of schemes, the paper has chosen to adopt FPGA+DSP system structure. Combined with extended functions, the paper has designed the demodulation system, which can detect and demodulate multi-pulse electron signals. The design of the system has provided foundation for the one on other miniaturization platform.(5) Based on FPGA, the paper has designed the circuits and optimized parts of the function units of carrier recovery algorithm and timing recovery algorithm, adopted VHDL language and transferred IP core to implement them. Based on the demodulation system, the paper has designed the prototype system and validated the two algorithms on it. The results prove the correctness of the design, and the process rate and area can all meet the system's requirement.