Design And Implementation Of Multi-thread Processor’s Instruction Dual-issue Structure

T2is a mulit-core multi-threaded processor. Each core includes eight threads whichare divided into two groups. In each group, FMT (Fine-grained MultiThreading) isemployed, and SMT (Simultaneous MultiThreading) is employed between groups. Eachgroup could issue one instruction every cycle. For a single thread, the maximum numberof instructions issued in one cycle is1, so IPC (Instruction Per Cycle) would not morethan one. Therefore, the performance of a single thread for T2is low.The performance of the single thread is an important element in the processordesign. One reason is that most application is serial, and the performance of thesingle-thread affects its executing speed. Another reason is that some parts of parallelapplications could not be paralled, which must be executed serially.In this paper, multi-thread dual-issue structure in T2is modified to supportsingle-thread dual-issue, which would improve the performance of a single thread. Themain contributions are as follows:1. Designing and implementing the single-thread dual-issue struction based on themulti-thread dual-issue structure in T2, to develop ILP (Instruction Level Parallelism) ina single thread and improve the performance of the single thread.2. Working out plans for the function verification and performance evaluation. Asoftware simulation platform is established and some function models for simulationsare constructed. The function verification points are extracted and the test stimulus areprogrammed according to them.3. Verifying and evaluating the single-thread dual-issue structure on the softwaresimulation platform. Results show that the designed structure achieves the expectedfunctions, and is able to improve the performance of a single thread.