UPF-based Logic Synthesis And Equivalence Checking In Low Power Design

With the developing of integrated circuit, chips require more and more power consumption, many low power design flow where generated. More and more chips produced by low power design methodology. UPF-based low power design methodology which produced by Synopsys Inc. are widely used in industry. It uses UPF, the uniform file format, to describe the low power intent of designs. UPF is used in every step of classic design flow, giving directions for the implementation of low power design intent.Logic synthesis is a process of transforming RTL design to netlists, and is a important step in RTL-GDSII flow. Timing, power, area and other design elements are optimized when synthesis. It's a complicated process, needing to apply reasonable design constraints to get good result. We must check whether timing and other constraints are met after synthesis.Equivalence checking verify function equivalence of designs with in design flow, through comparing different expression form of design. For example, we must verify whether RTL and post-synthesis netlists are functional equivalence.The thesis involves low power design implementation flow, UPF-based synthesis, equivalence checking, STA and so on, using the design of a low power wireless hand-held devices'chip SEP6010B as the object of research. Explored and completed UPF-based logic synthesis, equivalence check and resolved related problems by using Design Compiler and Formality. From the test result after taped-out, we well achieved the low power intent of the design, and confirmed the validity of UPF-based low power design methodology.