The Research Of Face Detection Algorithm And Its FPGA Design

Face detection is to determine the location, size, and posture of all existing facefrom the input information (image) in any face recognition system, and it is a veryimportant step of the automatic face recognition system. With the great developmentof computer science in the field of human-computer interaction, face detection gainswide attention. Now, it has been successfully applied in intelligent video surveillance,cross-border management, e-commerce and other fields. This thesis studies the facedetection algorithm of AdaBoost and neural network, and analyzes and compares theiradvantages and disadvantages, then proposes an improved detection algorithm. In thepractical application, people often expect to have an independent, embedded facedetection system. So this thesis also proposes a hardware and software coordinationface detection system based on FPGA. The main contents of this thesis are asfollowing:1. This thesis, combining AdaBoost algorithm and neural networks (NN),proposes a new face detection method. First, all the face image data is normalized,then NN trains a series of weak classifiers, finally AdaBoost algorithm improves theaccuracy of weak classifiers to achieve face detection. The experimental results showthat AdaBoost-NN algorithm has better robustness and higher detection rate，and theresult is more objective and reasonable. Also, AdaBoost-NN algorithm is compared tothe algorithm which combines neural networks and gabor wavelet transform. Theresults show that, considering both the detection and time, AdaBoost-NN facedetection algorithm is better than Gabor-NN algorithm.2. Adopting XUP Virtex II Pro FPGA of Xilinx Inc as the development platform,this thesis implements face detection with the pure software method on PowerPC andMicroBlaze respectively, then compares the execution time of these two methods.3. This thesis also proposes an embedded face detection method based on thecooperation of hardware and software. First, based on PowerPC which is the centeralpart of XUP Virtex II Pro FPGA, a hardware platform is set up. Then, two mostcritical IP cores of this system, video input and display IP core with the rectanglefeature classification IP core, are designed. In order to improve the speed, the featuredata is stored in the BRAMs. Also, in the feature classification IP core, a parallelprocessing method is used. The final simulation results show that the detection speedis significantly increased compared to the implemention of software. And the whole system is relatively flexible. For different applications, the software processing partjust needs to be simply changed.