VLSI Design Research And FPGA Implementation Of Adaboost Algorithm

With the development of computer science, face detection, which is one of the essential part in face information processing, has been a basic and important research theme in the field of pattern recognition, computer vision and human-computer interaction. However, the face detection algorithm has some disadvantages, such as large amount of computation, low detection speed, etc. It's too slow to meet real-time detection requirement if it's implemented in software, and It costs too much resources if it's implemented in hardware.In order to overcome the disadvantages of current hardware implementation of face detection algorithm, this paper presented a dual-pipeline detection architecture based on careful analysis of the Adaboost algorithm and its current hardware implementation. The proposed architecture has been successfully implemented on Virtex-II Pro FPGA platform, and the whole system could meet the real-time request. The detail work and innovation includes are as the following:Basic principles of face detection and some classic algorithms are introduced, in which the Adaboost algorithm has been introduced in detail.Detailed analysis has been taken on the current architecture, and two main disadvantages are revealed, which are low detection speed and high resource occupation. In order to deal with these disadvantages, a dual-pipeline architecture is presented. The proposed architecture consists of a pipeline of scan window and a pipeline of feature. It is suitable for embedded implementation. After the working flow is showed, another improved architecture with pre-load is presented to speed up the detection process. Comparison based on four criteria is taken on the current architectures and proposed architectures. The criteria are RAM accessing efficiency, quantity of store units, detection speed and quantity logical unit. All these comparisons show that the proposed architecture is better than all the current ones.This paper also gives a detailed VLSI implementation of the proposed architecture. The whole design is divided into several sub-modules from top down. Each sub-module is showed in detail with hardware structure, FSM, and simulation waveform.The whole implementation is emulated on Vertex-II FPGA platform from Xilinx. The emulation result showed that with the input video in QCIF format, the face detection system can run at a detection rate of 50fps.