Study Of The Reliability Of The Gate Oxide Related To EEPROM

Nowadays, Non-Volatile Memory is facing the same reliability problem like other semiconductor devices with the devices'scaling down. Because of EEPROM operating under the high electric field frequently, it attracts much more attention to its oxide quality and stress-induced degradation problems, which have become one of the most important issues in its developing process.The dissertation discusses briefly the reliability issues and its mechanism of EEPROM at first. The retention characteristic of EEPROM has been studied by high-temperature and electric stress accelerated tests. In high-temperature stress accelerated test, a predictable model for evaluating EEPROM retention characteristics is developed based on the theoretical analysis and experiments results. The time and temperature dependency of threshold voltage shift exhibits two distinct phases. In electric stress accelerated test, the model is analyzed by assuming that FN tunneling is the charge leakage mechanism, which describes the relation of threshold voltage shift and stress voltage. It is concluded that the threshold voltage shift is linear with stress time in the log-log scale. Moreover, the slope of the shift is variable with the applied stress voltage changes.The dissertation investigates the effect of the degradation of gate oxide to device performances by the study on SILC (stress-induced leakage current) of the ultra-thin oxide with NMOSFET.For the ramp voltage stress I-V measurements, the relations of gate current to gate voltage are different related with the oxide thickness, which is caused by the distinct origins of the tunneling current for different oxide thickness. Furthermore, the breakdown characteristic of the oxide is getting worse under high temperature.For the constant voltage stress experiments, it is found that the threshold voltage shifts along the stress time has a turnaround phenomenon with 4nm gate oxide devices when negative gate voltage stress is applied. It can be explained that positive charge trapping is dominant at the early stage of stressing, and negative charge trapping are becoming prominent as the stress time increases, causing the turnaround of the shift. However, threshold voltage shift is always positive-direction and exponential to stress time with 1.4nm gate oxide devices, which is due to the influence of interface trap becoming prominent compared with trapped charge as the oxide thickness decrease. The experiments of GIDL (gate-induced-drain-leakage) stress have also been carried on with LDD NMOSFET to understand the GIDL tunneling effect on devices. The results shows that in the 1.4nm and 4nm gate oxide devices, the GIDL tunneling current decreases with stress time increasing, which proves that the oxide trapped holes are generated by GIDL stress. Besides, the threshold voltage shifts along the stress time shows different phenomena depending on oxide thickness, which is induced by the different effects of the holes near overlap region and interface traps to the threshold voltage.