Study On IP Of Real Time Clock

As the development of the design and manufacture technology of nano-meter Integrated Circuit(IC), IC has come into the high-speed SOC (System On Chip) age. Higher request has been brought forward to the capability of the chip system, and scale of SOC is increasing for the demand of the information industry and market. The design problem is not whether a chip is able to accommodate to the system design, but whether the design can catch up with the increasing speed of complexity for a chip and meet the requirements that the market competition is strict with the time that produces come into market. Nowadays, a design based on chip cores has become a trend towards the EDA development. It is promising to develop IP (Intellectual Property) cores with independent intellectual property right.We have done some research on an IP core design of real time clock RTC based upon the intelligent monitor system SOC. A reused IP soft core is designed for the RTC module under the key design method and technology of the reused IP core. Firstly, the total clock system was divided into several function modules, whose functions and arithmetic were introduced. And then, through discussing the way of low power design in SOC and synthesizable coding, we used the IP core reuse technology and VerilogHDL, described the design of the modules by the high-level synthesis and simulated the system by the EDA. The design of RTC module's IP soft core was finished.The key problem of the paper is the research of the multi-clock system and technology design, plus the problems during the design. The basic is the RTC IP soft core design. We introduced the clocks in the digital circuit design and presented some met-stable state phenomenon of the multi-clock system and how to solve. Considering the stability of the system and the met-stable state phenomenon in multiple clock system, the synchronous way of asynchronous control signal and the data path are researched, and we did some research on the design method of many synchronous circuits design and RTL, compared some kinds of clock system signals and summarized the clock design of the SOC. All above are the creative points of the paper.