Design And Research On AVS And H.264/AVC Video Decoder

In the past ten years,digital video technology has been widely used in field of computer,communication,TV,broadcast,which has brought a series of new applications such as TV conference,videophone,digital TV and so on.In recent years, with the development of digital audio video codec technique and VLSI,AVS and H.264/AVC have represented a new generation of video coding standard and become to be the mainstream.By introducing the latest video coding technology,AVS and H.264/AVC gain a wonderful coding efficiency.However,the improvement of compression efficiency is based on the cost of the complexity of compression algorithm.For high-definition television,it is difficult to achieve real-time by software decoding.That makes it is difficult to achieve real-time decoding only by software.Especially high-definition television,hardware accelerator or appropriative hardware decoding circuit is necessary.Considering above situation,ASIC implementation is the best program for decoder design.By investigating AVS and H.264/AVC standards,similarities and differences about algorithm of two standards are summarized in the thesis.Furthermore,system design scheme of multi-mode decoder is proposed through the way of Hardware/Software Partitioning,and reasonable hardware modules partitioning is carried out through the way of advanced design methods,such as parallel design,data drive technique and so on.The research on multi-standard and configurable video decoder is helpful for the design of AVS SDTV/HDTV video codec chip and for the industrialization of AVS standard consequently.In order to improve decoder flexibility and promote AVS standards to more fields, the thesis also makes a deep research on decoder output module DF and proposes the hardware architecture for multi-channel parallel output.This architecture adopts an efficient method for multi-channel parallel frame buffer and three-level buffer-on-chip,which can reduce 25%of memory data bandwidth and improve nearly three times of reading speed.The decoder can output a number of pictures onto a monitor,or onto several monitors.DF design is implemented by Verilog HDL, simulated by Modelsim and successfully verified on Altera FPGA verification board. The multi-channel pictures are displayed on the high-definition television can prove this design functional correctness.So the multi-mode decoder with new DF design can be applied to the field of digital video monitor.