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OFDM Based Chip Design Of Receiver Baseband

Posted on:2010-05-27Degree:MasterType:Thesis
Country:ChinaCandidate:J P LiuFull Text:PDF
GTID:2178360275473503Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
ABSTRACT:OFDM(Orthogonal Frequency Division Multiplexing) is a high speed transmission technology.The sub-carriers of the system are orthogonal,so their frequency spectrum utilization is effective.Also because of the ability of anti-mulitpath and anti-frequency selective channel,it is the 4G key technology and the hot research topic.In this paper,we study the wirelesss communication baseband system base on OFDM,the frame structure of our OFDM system is similar to the one of IEEE802.11 a. First model the system with matlab,the channel is AWGN,multipath and small frequency offset.In the receiver model,we use the double window detection algorithm to synchronize the frame,long train sequence max interrelated value to synchronize timing,short train sequence delay interrelated to synchronize carrier frequency,pilot channel to correct the phase offset,use 64-point FFT to demodule,use QPSK to map the bits,use viterbi decoding,and get the transmit bits.The bit rate depends on the way of convolutional encoding,the number of the data subcarriers and the way of code maping.And then implement the OFDM receiver baseband base on the algorithm of the model.The design is stream line style and process the signal in real time.The baseband includes frame detection module,carrier frequency synchronization module,timing synchronization module,64-point FFT module,channel estimation module and Viterbi decoding module.And simulate the hardware with the test data generated by the model above to verify the correction of the hardware design.After the timing simulation on FPGA,we do the back end design with TSMC 0.18um process.We use Synopsys Design Compiler to synthesize,Cadence Encounter to auto place and rout,and get the layout.And then extract the standard delay file for the back end simulation.In the paper,we select the suitable algoritnm,implement the hardward,simulate and generate layout which go through the entire flow of chip design.At last we get a chip of 31mm~2 which dissipate 875mW.Because of the ideal channel environment,we get no error bit in the back end simulation which realize the predefine function.
Keywords/Search Tags:OFDM, VLSI, Receiver baseband chip, FFT, Viterbi
PDF Full Text Request
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