Algorithms And VLSI Architechtures For An OFDM-based Broadband Wireless Baseband Receiver

With the rapid growth of digital wireless communications in recent years,the need for broadband or high-speed data transmission is increased.Moreover,future wireless systems are expected to support a wide range of services that include video,data and voice.OFDM (orthogonal frequency-division multiplexing)is a promising candidate technology for achieving high data rates in wireless environment,due to its high spectral efficiency and its strong resistance to inter-symbol interference(ISI),which is a common problem found in high-speed data communication.The digital OFDM baseband receiver,one of the key parts in an OFDM system,plays a vital role in determining the overall transmission performance. This thesis is focused on addressing many design issues for a high-performance digital OFDM baseband receiver,which mainly includes;design of a synchronization scheme and its key algorithms,design of an equalization scheme and its key algorithms,and VLSI design aspects related to these receiver algorithms.Research results of the thesis are expected to constitute a technical foundation for designing an OFDM-based broadband wireless ASIC.In this thesis,a synchronization scheme suited for packet-based OFDM systems is proposed.It consists of the estimation of synchronization parameters in the initial acquisition stage and the elimination of residual synchronization errors in the tracking stage. Many practical algorithms for the initial estimation scheme,such as the fast symbol timing, the time-domian carrier frequency offset(CFO)estimation and the frequency-domain search for the integer frequency offset,are proposed.Simulation results show these algorithms are effective and efficient.Despite fine estimations used in the initial acquisition stage,there still exist residual synchronization errors.Even though these errors are very small,they severely degrade the overall bit error rate(BER)performance.In this thesis,an efficient all-digital elimination scheme for residual synchronization errors is proposed aiming to improve the overall BER performance.It consists of two loops;a pilot-aided timing error tracking loop and a pilot-aided frequency error tracking loop.It has the canonical architecture,but two new techniques are devised for this scheme to achieve improvement on existing systems.One is the pilot-aided reeursive algorithm for joint estimation of the carrier-frequency and sampling time offsets.Systems with a small number of pilots per OFDM symbol usually adopt an averaging-based LS line-fitting method or its weighted version for offset estimation.This line-fitting estimator has a very slow response to changing parameters as well as a large data storage requirement.The proposed estimator is based on the recursive least-squares(RLS)algorithm,which can recursively estimate residual synchronization errors in an adaptive fashion.It also requires less storage than the conventional estimators. Another novel technique is the delay-based timing error correction.Unlike the popular NCO-based timing error correction,it can resample the incoming data stream without introducing any sampling disturbance.It is also easier to implement than the existing techinques.Channel estimation and equalization is another important issue in the OFDM receiver design.In this thesis,an adaptive frequency-domian equalization scheme which can work well in time-variant channels is proposed.It is composed of a one-tap frequency equalizer and a channel gain updater which is responsible for tracking the dynamic channel state.The channel update process is decision-directed,approximating the latest channel state information from the slicer's output and the received symbol data according to the RLS criterion.Compared with the conventional least-mean-squares(LMS)algorithm,the RLS channel update algorithm offers better ability of tracking time-variant channels despite some computational complexity.VLSI design aspects related to the receiver implementation are also investigated in this thesis.Many VLSI architectures are devised to implement the OFDM receiver algorithms. Digital logical design and FPGA synthesis are done to evaluate the hardware efficiency for these VLSI architectures.Numerical simulations are performed on an OFDM baseband receiver incorporating the synchronization and equalization schemes proposed in this thesis.The effectiveness of both schemes is justified by various simulation results.It is also demonstrated by simulations that the adoption of the residual synchronization error elimination and adaptive equalization schemes can improve the OFDM receiver's overall BER performance.As the SNR gets higher,the improvement become more obvious,and it can reach 7 to 8 dB in BER reduction at most.