The Realization Of Adaptive Arithmetic Coder With FPGA

With the development of technology of multimedia, the higher and higher speed of image processing is required. Image compression is an important part of image processing. The new arithmetic appeared, but the new arithmetic of compression is also more complex, the speed of image coder realized by software becomes slower. The speed of adaptive arithmetic coding is a bottleneck of JPEG2000. It is not so real time in despite of the quick development of computer. FPGA is an excellent tool for high speed image processing, because it's pure hardware and can work in parallel way with very high speed. So it has a considerable significance to realize adaptive arithmetic coder .A high-rate method of realizing adaptive arithmetic coding with FPGA is given. This method adopts three improvements. It is realized with VHDL language.First, the coder generally can't adopt pipelining structure as there is a feedback in it. In order to process a data in one clock, the coder is divided into two parts, the first part works after the rising edge of clock, another works after falling edge of clock.Second, there is a very long logic time delay, so a feedback forecasting technique is added to solve this problem. To coordinate with the feedback forecasting technique and make it easy to realize with FPGA, this thesis changes the structure of adaptive arithmetic coding.Third, this thesis eliminates a loop which possible runs many times using a way of calculating the times of the loop; it increases the frequency of clock in a large extent.This thesis realizes the adaptive arithmetic coding which is not improved with C language, compare with the result of simulation of improved adaptive arithmetic coder and indicates that the output of improved coder is correct. The frequency of clock can reach up to 50M/s and it can processes a data in one clock. It uses about 800 CLBs (Configurable logic block).