Research And Implementation Of Adaptive Multi-alphabet Arithmetic Hardware Coder With Sliding Window

With the rapid development of information and network technology,data has been one of the main topics nowadays.The scale of data is becoming larger day by day when people enjoy the convenience brought by technological progress.Therefore,data compression has become an important research on Information Science.Data compression refers to representing original data on a smaller scale without losing useful information.According to whether the decompressed data can be completely restored to the original data,data compression technology can be divided into lossy compression and lossless compression,for some scenarios that do not require the complete restoration of the original data,like video and photo,it can utilize lossy compression to satisfy the data requirement.For some scenarios that are particularly sensitive to data,such as case samples in medical research,genetic information in biological sciences,lossless compression is particularly important.Arithmetic coding is not only a lossless compression method,but also an optimal coding method close to the entropy.Compared with other entropy coding methods,arithmetic coding can achieve better coding.Arithmetic coding has formed many famous coding schemes with years of development.Like QM-coder in JPEG,MQ-coder in JPEG2000,CABAC in HEVC and GVSW(Generalized Virtual Sliding Window).Although arithmetic coding can achieve better compression,its coding speed is very low.In order to solve the above contradictions,this paper chooses advanced GVSW arithmetic coding as the software scheme,and uses FPGA as the hardware platform to achieve high rate acceleration of GVSW arithmetic coding,so that it can meet the increasingly severe compression requirements.GVSW arithmetic coding is a multiplication-free coding scheme proposed in recent years,which has better coding effect than most arithmetic coding schemes.However,due to its sequential coding process,serial mode of work and relatively large cyclic iteration,its software implementation can not achieve a satisfied coding speed.For ASCII,the coding speed of GVSW arithmetic coding is about 520(8(87)0)/8)(77),and there is strict sequence and data dependencies between probability updating,probability estimation and proportional normalization in software schemes,which makes the coding efficiency of GVSW arithmetic coding inefficient on platforms such as CPU.In order to give full play to the characteristics of FPGA parallel execution when implementing GVSW arithmetic coding hardware coding system,this paper proposes an accelerated algorithm PUSW(Parallel Update of Sliding Window) based on parallel update sliding window to solve cyclic iteration.Due to the serial encoding mode between software modules,this paper resigns a parallel encoding mechanism suitable for hardware implementation and determines the configuration of additive trees,which is suitable for the cumulative sum of GVSW arithmetic coding,and utilizes the data distribution characteristics of encoding process to develop a step output strategy to optimize the proportional renormalization process,which greatly improves GVSW string and decrease sequential work mechanism.According to meet different levels of GVSW software scheme,two levels of hardware coding system has been implemented in this paper.And serial port is used as an external interface with GVSW hardware arithmetic coding system that has been completed on FPGA.In the condition of the same result of hardware coding and software coding,the hardware coding system can achieve the increase of coding speed moreover 90 Mbps.Compared with software implementation,hardware implementation of level 8 can achieve about 2282 times of the acceleration and hardware implementation of level 3 can achieve about 2380 times of the acceleration.