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Desiging Of Low Power Ternary CAMs In NOR Type

Posted on:2010-12-27Degree:MasterType:Thesis
Country:ChinaCandidate:Y Q YangFull Text:PDF
GTID:2178360272999577Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapidly growing number of Internet users,as well as the boom of using the network applications,a high-speed network is widely asked for.Transmission materials have already reached the demand for high-speed network,the key of the restriction of the speed of network transmission lies in the transmit speed of the transmission nodes(routers, switches) The new IPv6 protocol requires a longer IP address and a faster transmission speed,so the design of a high-speed low-power transponder module can resolve this problem.This thesis is based on the chip of the ternary content addressable memory,solves the problem of finding and forwarding the address.TCAM is a "digital shield" feature of the hardware look-up table,it can achieve large-scale calculating in a clock cycle,which is ideal for network applications.In order to reduce power consumption of the TCAM chips,first of all,512~* 144 chip should be separated into 8 small pieces,with the size of 64~* 144 as a whole,each piece has a small independent operation of the properties.In most cases only one of them need to be activated.During the integration of the chip-system only one simple connection is demanded.TCAM power consumption is mainly in the search operation,his paper also carried out each small piece of architecture-level and circuit-level optimization.In the architecture-level optimization in the search line to block the strategy,as well as pre-match line search.The main search of the two search methods to increase the speed at the same time reduce power consumption in the circuit-level optimization of a matching line MLSA sensitive amplifier and a charge sharing circuit to further reduce the power of search.The paper also optimizes the priority encoder of TCAM in a low-power-consumption way to reduce the power consumption of other uses besides the searching as much as possible.Cadence IC50 systems is a simulation of the designed circuit,and achieved better results.The power consumption of one-time 8~*144 bits TCAM searching is 26.09mW,the working speed can reach more than 62.5 MHz.
Keywords/Search Tags:Ternary Content Accessible Memory, Low power design, Dynamic Circuit, MLSA
PDF Full Text Request
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