Research On Digital Processing Unit In UHF RFID Tag

RFID (Radio Frequency Identification) is a new technology. It integrates some latest technology, such as computer science, information processing, wireless communication, automatic mechanics and etc. RFID system is typically composed of reader and tag. The tag which is attached to the identified objects stores data in defined format. Reader and tag can communicate with each other by advanced radio frequency technology according to certain protocol. With merits of waterproof, antimagnetic, safe and convenient, RFID is widely used in many fields such as logistics, retail business, transportation, manufacture, communication and etc.The thesis firstly introduces RFID principles and architectures, and analyzes the ISO/IEC 18000-6 Type B/C protocol. Digital part for UHF tag compatible with ISO/IEC 18000-6 Type B/C protocol was designed. The chip of Type B tag was implemented with Chartered 0.35μm 3.3V CMOS technology. The area of layout was 584.8×576μm2, and power analysis using Power Compiler showed that power consumption of digital part was 41.2μW under clock frequency of 500KHz and operating voltage of 3.3V. The tests were done on both FPGA platform together with analog front-end circuit and the fabricated chip, whose results showed that the circuit met the requirements of the protocol and had correct function. Architecture design and RTL model creation of digital part conformed to Type C protocol were finished. Simulation results showed that the logical function of the design was correct.Moreover, low power methodology was worked over. Some low power design techniques like architecture optimization, clock management, gated clock for sub-modules and algorithm optimization were used when designing the digital part. Finally, the available and effective low power methods were summarized.