The Design And Implementation Of Circuit For Image Denoise Based On ASIP Array

It brings inconvenience to the later processing for the introduced noises while in the acquirement of CCD Image, thus image denoise is necessary. According to the massive data and real-time capability of the image processing system, the traditional CCD Image denoise implementation can not meet the requirements.ASIP(Application Specific Instruction set Processor) fills the gaps between digital signal processor(DSP) and application specific integrated circuit(ASIC). It has flexible solutions the same as that offered by DSP while avoiding the highly price cost. It has the highly optimized platforms the same as ASIC while avoiding the lower flexibility. In recent years, ASIP is becoming a new study field of hardware realization, and with the development of the ASIP array structure, it provides a new approach for the real-time processing system of the massive data.This article is based on a real-time processing system for CCD Image. According to the character of the images, we proposed an ASIP array design based on RISC architecture for image denoise in the project. A 16bit single cycle single instruction ASIP processor was realized using hardware description language VerilogHDL based on Xilinx FPGA Virtex5 LX85. After that, with the knowledge of the parallel processor system, we designed a distributed memory MIMD ASIP array processor. In addition, we made simulation on the ASIP array processor with the image denoise algorithm based on 5/3 lifting wavelet transform, and the results showed that our design was correct and effective. At last, on the basis of the fully completed of the code of the ASIP array processor, we gave out the design and realization of the circuit of the processor and its signal integrity analysis.