Research On Intelligent Edge Processor Based On RISC-? And FPGA Implementation

In recent years,with the development of deep learning,hardware acceleration of convolutional neural networks has become a hot research topic,especially at the edge,which requires higher real-time performance.Therefore,the reconfigurable neural network accelerator and the general-purpose CPU are combined to construct a So C acceleration method,which is versatile and can be optimized for specific problems.However,the traditional CPU instruction set architecture ARM and x86 are not open source,resulting in expensive patent licensing fees.Therefore,the open source instruction set architecture + accelerator model represented by RISC-? combined with the fully automated design method helps Design CNN acceleration platform more efficiently.To this end,this thesis proposes a convolutional neural network accelerator based on the RISC-? open-source instruction set architecture and its hardware design,and builds a face recognition network to test the architecture.First,the face at the edge is affected by the light,expression,and large posture changes,resulting in a sharp drop in the recognition rate.Therefore,this thesis improves the SqueezeNet neural network to improve the recognition rate,mainly considering the characteristics of the ResNet network,adding a residual module to the SqueezeNet network to improve the recognition rate of the network.Finally,the network is tested in the intelligent edge processor designed in this thesis,mainly to test the performance of the processor.For the intelligent edge processor,this thesis designs the acceleration unit of the convolutional layer,and then builds a hardware acceleration system based on the RISC-? open source instruction set.According to the characteristics of FPGA parallelism,this thesis designs the acceleration unit of the convolutional layer,uses the loop unrolling strategy to design the PE array,and accelerates the calculation of the convolutional layer through the parallel calculation of the PE array.The ROCC interface used in this article is based on the RISCV processor to communicate with the designed convolutional layer accelerator,and the instructions of the ROCC interface are defined.The processor sends corresponding instructions through the ROCC interface to control the operation of the accelerator.In order to reduce the consumption of hardware resources and increase the processing speed,this thesis quantifies the feature map and weight value,and adopts a circular block strategy and double buffering in the system.Combine the entire design with the RISC-? core to build an So C for testing.This article simulates the entire design in the Rocket-Chip generator.First,the entire system is tested in the C++ simulator under Linux,mainly to test the acceleration effect of the acceleration module.The second is a hardware resource test in vivado.The experimental results show that the calculation time consumption after using the CNN accelerator is increased by 10 to 40 times compared to when the processor is only used for calculation.Finally,it is tested in FPGA,and the result of the test shows that the consumption of hardware resources is within an acceptable range.