Research And Implementation Of Echo Canceller Based On FPGA

Echo canceller, a working cell that cancels electrics echo or acoustics echo in communication systems, has important application in systems such as hand-free telephone, wireless product, IP telephone, audio conference and so on.Traditional echo canceller is usually implemented on general DSP processor. Such echo canceller can satisfy requirement of echo cancellation performance on this condition that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet the requirement of real-time processing. FPGA which is bulky and high-performance makes up for the deficiencies as mentioned above. Implementing digital signal processing based on FPGA can resolve problems of both parallel and speed. The characteristic of flexible reconfiguration makes that DSP system easier to implement, test and upgrade.This thesis is focused on electrics echo canceller in PSTN. An applied adaptive echo canceller based on FPGA platform is designed and implemented. During the process of implementing the whole echo canceller system, The following research works are carried out.Firstly, all models of the echo canceller are thoroughly researched and completed using C language. Integrated with application, we put more emphasis on the adaptive filtering algorithms including LMS, NLMS, DLMS, which can get a tradeoff between the convergence performance and the computational complexity.Secondly, the Altera StratixEP1S25DSP development board and Verilog Hardware Description Language are introduced. Combined with the integrated developing environment Quartus II, the flow of FPGA design is also described.Finally, after the total design scheme is given, all models are implemented on FPGA platform using Verilog Hardware Description Language. The whole echo cancellation system is functional and timing simulated in Quartus II environment. Simulation results and relevant performance are given too.