Research On Adaptive Echo Cancellation And FPGA Implementation

Echo canceller is widely used in PSTN system, mobile communication system, video teleconferencing system, and other speech telecommunication fields. In PSTN system, because of the resistance matching problem, signal leakage is generated and reflected to the far-end when the far-end signal go through the hybrid, which is called line echo, and the existence of line echo will seriously affect the quality of speech communication. This paper primarily studies on line echo cancellation technology, and proposes a system implementation solution based on the platform of FPGA which satisfies the demands for practical application.In accordance with the generating principle of line echo and after analyzing main echo cancellation algorithms, and after in-depth study on the core algorithms of all the module of adaptive echo canceller, in particular, adaptive filtering algorithm and double talk detection algorithm, considering with complexities and capabilities of all the candidates, this paper chooses NLMS algorithm to implement echo canceller. In order to improve traditional double talk detection algorithm easily leads to misjudging when near-end speech signal amplitude is low, this paper proposes an improved algorithm on double talk detection based on sub-band filter banks.This paper first completes C program version of all the echo cancellation algorithm modules, including the adaptive filter, far-end detection, double talk detection, non-linear processing and comfort noise modules. The results of simulation tests prove that the algorithm modules effectively improve the performance of echo cancellation.On the basis of C program version, all the hardware modules of the algorithms are completed, using Verilog HDL hardware description language. The hardware modules of the algorithms achieve through module-level and system-level functional simulation, timing simulation on the software platform of Quartus II and ModelSim, and ultimately this paper achieves the system based on FPGA hardware platform. This paper elaborates on FPGA-based design flow and design methods, and describes the adaptive filter algorithm, FIR filter based on distribute arithmetic, divider and finite state machine design process.According to the ITU-T G.168 standard, large numbers of subjective and objective testing is completed on the FPGA-based adaptive echo cancellation system, which is proved effective on echo cancellation and the test results meet or even surpass the demands of ITU-T G.168 standard.