Designing And Implementation Of Echo Canceller Based On FPGA

In system such as handfree telephone, wireless production , IP telephone , ATM speech service, telephone conference and so on echo cancellation theory has its important application. The solution of echo canceller is different in some way. This paper is focused on electrics echo canceller in PSTN. Electrics echo is produced because impedence is unsuited when speech signal transmitted in PSTN.Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA which has large capacity and high speed overcome the deficiencies as before mentioned. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to amend, test and promote.In this thesis, Echo canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:1 .Researched all modules of adaptive echo canceller include adaptive filter, far detector, double talk detector, NLP, comfort noise generator, and then implemented using C language.2. Researched flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.3.The whole system is functional and timing simulated in both ModelSim and Quartus II environments, and implemented in FPGA hardware platform.4.According to ITU-G.168, this echo canceller get kinds of testing. All the testing achieve desire.