Research And Implementation Of Echo Canceller Based On FPGA

Echo Canceller is a function cell which cancels electric echo or acoustic echo in communication systems. In many systems, such as handfree telephone, wireless production , IP telephone, ATM speech service, telephone conference and so on, echo cancellation technique has its important application.For the various solution of echo canceller are different, this thesis is focused on electric echo canceller applications in PSTN. Electric echo is caused by the impedence mismatch during the transmission in PSTN. Electric echo canceller can synthesize a replica of the echo and subtract it from the real echo according to reference signal.Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion which requires low real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA with large capacity and high speed can overcome the deficiencies as mentioned above. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to modify, test and promote.In this thesis, Echo Canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:(1). Research_all modules of adaptive echo canceller including adaptive filter, far detector, double talk detector, and then implement them using C language.(2). Research flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.(3). The whole system is functional and timing simulated in QuartusⅡenvironments, and implemented in FPGA hardware platform.(4). According to ITU-G.168, this echo canceller gets kinds of testing. All the testing achieve desirable requirement.